The present invention concerns a Dynamic Random Access Memory (DRAM), and particularly, a circuit arrangement of bit lines therein.
Generally, a DRAM comprises a plurality of bit lines of a same length arranged in parallel with each other, and a plurality of flip-flop sense amplifiers connected with each of the bit line pairs. The memory cell comprises one transistor and one capacitor. Between each bit line and each word line is connected a memory cell, so that all the connected memory cells are arranged in a matrix of rows and columns. The circuit arrangement of the bit line pairs and the sense amplifiers conventionally appears in two forms. Namely, one form is called an open bit line arrangement wherein each of the sense amplifiers is disposed at the center of each bit line pair, while the other is called a folded bit line arrangement wherein each of the sense amplifiers is disposed at one end of each bit line pair. However, considering the equilibrium of the bit lines and the high density circuit arrangement of the memory cells, the folded bit line method is mainly used. Nowadays, as the memory cells in the DRAM are highly integrated, the space between the bit lines becomes narrower and the storage capacitor of the memory cells also becomes smaller. Hence, when a memory cell is accessed and a sense amplifier operates in corresponding to the bit line connected with the memory cell accessed, the mutual coupling capacitance between the bit line and its upper and lower adjacent bit lines may affect its normal operation.
For example, FIG. 1 exemplifies a conventional folded bit line circuit arrangement. The memory cells MC10-MC12 and MC20-MC22 are connected with the intersection points of the bit lines B0-B2 and B0-B2 and the word lines W1 and W2, and each of the bit line pairs B0--B0, B1--B1 and B2--B2 is connected, at each end, with corresponding one of the sense amplifiers SA0-SA2. Each of the memory cells MC10-MC12 and MC20-MC22 comprises a MOS transistor M and a storage capacitor C connected in series with the drain-source path of the transistor. Each of the drains of the MOS transistors is connected with one of the bit lines B0, B0, . . . B2 and B2, while each gate of the memory cells MC10-MC12 and MC20-MC22 is connected with one of the word lines W1 and W2. The other end of the storage capacitor is connected with a constant voltage Vp. It is assumed that the parasitic capacitance of each bit line is CB, the mutual coupling capacitance between the adjacent bit lines is CC, and the capacitance of the storage capacitor C is CS.
If the memory cells MC10-MC12 are chosen by the word line signal applied to the word line W1, electric charges stored into the storage capacitors of the memory cells are respectively transferred through the corresponding MOS the bit lines B0-B2, so that the voltage of each of the bit lines B0-B2 becomes higher or lower by the amount of ##EQU1## than the voltage of each of the other bit lines B0-B2, wherein VS is the voltage of the storage capacitor, and VBL is the bit line voltage prior to selecting the memory cell. If the memory cells MC10-MC12 cause the bit lines B0-B2 to have the voltage higher by .DELTA.VS than the voltage of the bit lines B0-B2, the sense amplifiers SA0-SA2 are activated so that the voltage of the bit lines B0, B1 and B2 having a low voltage of VS is lowered. Hence, the voltage of the bit line B1 is lowered due to the influence of the coupling capacitance CC resulting from the lowering of voltages of the adjacent bit lines B0 and B1. Such an adverse effect increases as narrowing of the space between the bit lines, resulting from increasing of the memory density. Further, if the capacity of the memory cell is reduced, the sense amplifier is liable to malfunction due to the coupling capacitance.